/* FIXME: Moved this test to here to avoid stopping simulation if there are actions running on cpus and all cpus are with availability = 0.
* This may cause an infinite loop if one cpu has a trace with periodicity = 0 and the other a trace with periodicity > 0.
* The options are: all traces with same periodicity(0 or >0) or we need to change the way how the events are managed */
/* FIXME: Moved this test to here to avoid stopping simulation if there are actions running on cpus and all cpus are with availability = 0.
* This may cause an infinite loop if one cpu has a trace with periodicity = 0 and the other a trace with periodicity > 0.
* The options are: all traces with same periodicity(0 or >0) or we need to change the way how the events are managed */