+ if(MC_state_interleave_size(state)){
+ MC_SET_RAW_MEM;
+ req2 = MC_state_get_internal_request(state);
+ req3 = *req2;
+ for(i=0; i<simix_process_maxpid; i++)
+ interleave_proc[i] = 0;
+ i=0;
+ interleave_size = MC_state_interleave_size(state);
+ while(i < interleave_size){
+ i++;
+ prev_req = MC_state_get_request(state, &value2);
+ if(prev_req != NULL){
+ MC_state_set_executed_request(state, prev_req, value2);
+ prev_req = MC_state_get_internal_request(state);
+ if(MC_request_depend(&req3, prev_req)){
+ XBT_DEBUG("Simcall %d in process %lu dependant with simcall %d in process %lu", req3.call, req3.issuer->pid, prev_req->call, prev_req->issuer->pid);
+ interleave_proc[prev_req->issuer->pid] = 1;
+ }else{
+ XBT_DEBUG("Simcall %d in process %lu independant with simcall %d in process %lu", req3.call, req3.issuer->pid, prev_req->call, prev_req->issuer->pid);
+ MC_state_remove_interleave_process(state, prev_req->issuer);
+ }
+ }
+ }
+ xbt_swag_foreach(process, simix_global->process_list){
+ if(interleave_proc[process->pid] == 1)
+ MC_state_interleave_process(state, process);
+ }
+ MC_UNSET_RAW_MEM;
+ }
+
+ MC_state_set_executed_request(state, req, value);
+