Replace while+modulo by a bitwise operation

[simgrid.git] / examples / msg / link5_state.trace

diff --git a/examples/msg/link5_state.trace b/examples/msg/link5_state.trace
index bc5ff5c..ac7300a 100644 (file)
--- a/examples/msg/link5_state.trace
+++ b/examples/msg/link5_state.trace
@@ -1,3 +1,3 @@
 0 1
-1.0 0
-10 1
+30 0
+35 1