Replace while+modulo by a bitwise operation

[simgrid.git] / examples / msg / tracing / procmig-deploy.xml

diff --git a/examples/msg/tracing/procmig-deploy.xml b/examples/msg/tracing/procmig-deploy.xml
index f13eace..bb317fe 100644 (file)
--- a/examples/msg/tracing/procmig-deploy.xml
+++ b/examples/msg/tracing/procmig-deploy.xml
@@ -1,5 +1,6 @@
 <?xml version='1.0'?>
-<!DOCTYPE platform SYSTEM "simgrid.dtd">
+<!DOCTYPE platform SYSTEM "http://simgrid.gforge.inria.fr/simgrid.dtd">
 <platform version="3">
   <process host="Fafard" function="emigrant"/>
+  <process host="Tremblay" function="master"/>
 </platform>