X-Git-Url: http://info.iut-bm.univ-fcomte.fr/pub/gitweb/simgrid.git/blobdiff_plain/9696c1a327d9f7439c42d72097c9eec20afb3c4a..2e7943186f8c5e75f1fc623d0f52ead2ae68f0fd:/src/surf/surfxml.l diff --git a/src/surf/surfxml.l b/src/surf/surfxml.l index f534db341f..1626cb523a 100644 --- a/src/surf/surfxml.l +++ b/src/surf/surfxml.l @@ -1,8 +1,8 @@ /* Validating XML processor for surfxml.dtd. - * Generated 2005/01/04 14:37:23. + * Generated 2005/02/10 12:28:10. * * This program was generated with the FleXML XML processor generator, - * (Id: flexml.pl,v 1.29 2005/01/04 09:30:15 alegrand Exp). + * (Id: flexml.pl,v 1.38 2005/02/10 11:13:51 mquinson Exp). * Copyright © 1999 Kristoffer Rose. All rights reserved. * * You can redistribute and/or modify this program provided the following @@ -25,9 +25,9 @@ /* Version strings. */ const char rcs_flexml_skeleton[] = - "$" "Id: skel,v 1.16 1999/12/09 04:01:51 krisrose Exp $"; + "$" "Id: skel,v 1.22 2005/02/10 11:18:26 mquinson Exp $"; const char rcs_flexml[] = - "$" "Id: flexml.pl,v 1.29 2005/01/04 09:30:15 alegrand Exp $"; + "$" "Id: flexml.pl,v 1.38 2005/02/10 11:13:51 mquinson Exp $"; /* ANSI headers. */ #include @@ -38,11 +38,10 @@ const char rcs_flexml[] = #include /* Generated definitions. */ -#define FLEXML_BUFFERSTACKSIZE 10000000 +#define FLEXML_yylineno +#define FLEXML_BUFFERSTACKSIZE 100000 /* XML processor api. */ -#include "surf/surfxml.h" - /* FleXML-provided data. */ const char* pcdata; AT_network_link_bandwidth A_network_link_bandwidth; @@ -51,18 +50,27 @@ AT_network_link_state A_network_link_state; AT_argument_value A_argument_value; AT_cpu_availability_file A_cpu_availability_file; AT_process_host A_process_host; +AT_route_impact_on_src A_route_impact_on_src; AT_route_src A_route_src; AT_network_link_latency_file A_network_link_latency_file; +AT_cpu_max_outgoing_rate A_cpu_max_outgoing_rate; +AT_route_impact_on_dst_with_other_send A_route_impact_on_dst_with_other_send; +AT_cpu_interference_send_recv A_cpu_interference_send_recv; AT_cpu_availability A_cpu_availability; +AT_route_impact_on_dst A_route_impact_on_dst; +AT_cpu_interference_recv A_cpu_interference_recv; +AT_route_impact_on_src_with_other_recv A_route_impact_on_src_with_other_recv; AT_network_link_name A_network_link_name; AT_route_element_name A_route_element_name; AT_cpu_power A_cpu_power; +AT_include_file A_include_file; AT_process_function A_process_function; -AT_cpu_state A_cpu_state; AT_route_dst A_route_dst; +AT_cpu_state A_cpu_state; AT_network_link_latency A_network_link_latency; -AT_cpu_state_file A_cpu_state_file; AT_network_link_state_file A_network_link_state_file; +AT_cpu_interference_send A_cpu_interference_send; +AT_cpu_state_file A_cpu_state_file; AT_network_link_bandwidth_file A_network_link_bandwidth_file; /* XML state. */ @@ -85,12 +93,13 @@ AT_network_link_bandwidth_file A_network_link_bandwidth_file; #define FAIL return fail static int fail(const char*, ...); +const char * parse_err_msg(void); /* Text buffer stack handling. */ char bufferstack[FLEXML_BUFFERSTACKSIZE]; char* limit = bufferstack + FLEXML_BUFFERSTACKSIZE; typedef struct BufferLast_s { - struct BufferLast_s *old; char* saved; char new[1]; + struct BufferLast_s *old; char* saved; char new1[1]; } BufferLast; BufferLast* last = (BufferLast*)0; char* next = bufferstack; @@ -100,14 +109,14 @@ char* next = bufferstack; #define BUFFERDONE (BUFFERPUTC('\0')) #define BUFFERLITERAL(C,P) bufferliteral(C,&(P),yytext) -static void bufferliteral(char c, char** pp, char* text) +static void bufferliteral(char c, const char** pp, char* text) { char *s = strchr(text,c), *e = strrchr(text,c); assert(s <= e); BUFFERSET(*pp); while (++sold = last; l->saved = p; - next = l->new; + next = l->new1; last = l; } @@ -147,6 +156,7 @@ static char* popbuffer(void) %option noyywrap /* Flex user-requested options. */ +%option yylineno %option nounput /* XML character classes (currently restricted to ASCII). */ @@ -184,6 +194,7 @@ Literal \'[^'']*\'|\"[^""]*\" */ %x PROLOG DOCTYPE EPILOG INCOMMENT INPI VALUE1 VALUE2 CDATA %x ROOT_platform_description AL_platform_description S_platform_description S_platform_description_1 S_platform_description_2 E_platform_description +%x ROOT_include AL_include S_include S_include_1 S_include_2 E_include %x ROOT_cpu AL_cpu E_cpu %x ROOT_network_link AL_network_link E_network_link %x ROOT_route AL_route S_route S_route_1 S_route_2 E_route @@ -202,7 +213,7 @@ const char* *statenames=NULL; /* Bypass Flex's default INITIAL state and begin by parsing the XML prolog. */ SET(PROLOG); /* FleXML_init */ - if(!statenames) statenames=calloc(IMPOSSIBLE,sizeof(char*)); + if(!statenames) statenames= (const char **)calloc(IMPOSSIBLE,sizeof(char*)); statenames[PROLOG] = NULL; statenames[DOCTYPE] = NULL; statenames[EPILOG] = NULL; @@ -217,6 +228,12 @@ const char* *statenames=NULL; statenames[S_platform_description_1] = "platform_description"; statenames[S_platform_description_2] = "platform_description"; statenames[E_platform_description] = "platform_description"; + statenames[ROOT_include] = NULL; + statenames[AL_include] = NULL; + statenames[S_include] = "include"; + statenames[S_include_1] = "include"; + statenames[S_include_2] = "include"; + statenames[E_include] = "include"; statenames[ROOT_cpu] = NULL; statenames[AL_cpu] = NULL; statenames[E_cpu] = "cpu"; @@ -244,7 +261,7 @@ const char* *statenames=NULL; /* COMMENTS and PIs: handled uniformly for efficiency. */ -{ +{ "