X-Git-Url: http://info.iut-bm.univ-fcomte.fr/pub/gitweb/simgrid.git/blobdiff_plain/1679193978528bbb628e0f3a7853cddf4f3cfe0d..b51da37243dc16575499f4cb7729fe8bdd7fa514:/src/mc/mc_state.cpp diff --git a/src/mc/mc_state.cpp b/src/mc/mc_state.cpp index 9df85bf8c6..59a9de060f 100644 --- a/src/mc/mc_state.cpp +++ b/src/mc/mc_state.cpp @@ -6,7 +6,7 @@ #include -#include +#include #include #include @@ -56,8 +56,8 @@ State::State() std::size_t State::interleaveSize() const { - return std::count_if(this->processStates.begin(), this->processStates.end(), - [](simgrid::mc::ProcessState const& state) { return state.isToInterleave(); }); + return boost::range::count_if(this->processStates, + [](simgrid::mc::ProcessState const& p) { return p.isToInterleave(); }); } Transition State::getTransition() const @@ -106,8 +106,7 @@ static inline smx_simcall_t MC_state_get_request_for_process( unsigned start_count = procstate->interleave_count; state->transition.argument = -1; while (procstate->interleave_count < - read_length(mc_model_checker->process(), - remote(simcall_comm_testany__get__comms(&process->simcall)))) + simcall_comm_testany__get__count(&process->simcall)) if (simgrid::mc::request_is_enabled_by_idx(&process->simcall, procstate->interleave_count++)) { state->transition.argument = procstate->interleave_count - 1; @@ -115,8 +114,7 @@ static inline smx_simcall_t MC_state_get_request_for_process( } if (procstate->interleave_count >= - read_length(mc_model_checker->process(), - remote(simcall_comm_testany__get__comms(&process->simcall)))) + simcall_comm_testany__get__count(&process->simcall)) procstate->setDone(); if (state->transition.argument != -1 || start_count == 0) @@ -181,7 +179,7 @@ static inline smx_simcall_t MC_state_get_request_for_process( state->transition.argument, sizeof(remote_comm)); mc_model_checker->process().read(state->internal_comm, remote( static_cast(remote_comm))); - simcall_comm_wait__set__comm(&state->internal_req, &state->internal_comm); + simcall_comm_wait__set__comm(&state->internal_req, state->internal_comm.getBuffer()); simcall_comm_wait__set__timeout(&state->internal_req, 0); break; } @@ -191,15 +189,13 @@ static inline smx_simcall_t MC_state_get_request_for_process( state->internal_req.issuer = req->issuer; if (state->transition.argument > 0) { - smx_synchro_t remote_comm; - read_element(mc_model_checker->process(), - &remote_comm, remote(simcall_comm_testany__get__comms(req)), - state->transition.argument, sizeof(remote_comm)); + smx_synchro_t remote_comm = mc_model_checker->process().read( + remote(simcall_comm_testany__get__comms(req) + state->transition.argument)); mc_model_checker->process().read(state->internal_comm, remote( static_cast(remote_comm))); } - simcall_comm_test__set__comm(&state->internal_req, &state->internal_comm); + simcall_comm_test__set__comm(&state->internal_req, state->internal_comm.getBuffer()); simcall_comm_test__set__result(&state->internal_req, state->transition.argument); break; @@ -207,16 +203,16 @@ static inline smx_simcall_t MC_state_get_request_for_process( state->internal_req = *req; mc_model_checker->process().read_bytes(&state->internal_comm , sizeof(state->internal_comm), remote(simcall_comm_wait__get__comm(req))); - simcall_comm_wait__set__comm(&state->executed_req, &state->internal_comm); - simcall_comm_wait__set__comm(&state->internal_req, &state->internal_comm); + simcall_comm_wait__set__comm(&state->executed_req, state->internal_comm.getBuffer()); + simcall_comm_wait__set__comm(&state->internal_req, state->internal_comm.getBuffer()); break; case SIMCALL_COMM_TEST: state->internal_req = *req; mc_model_checker->process().read_bytes(&state->internal_comm, sizeof(state->internal_comm), remote(simcall_comm_test__get__comm(req))); - simcall_comm_test__set__comm(&state->executed_req, &state->internal_comm); - simcall_comm_test__set__comm(&state->internal_req, &state->internal_comm); + simcall_comm_test__set__comm(&state->executed_req, state->internal_comm.getBuffer()); + simcall_comm_test__set__comm(&state->internal_req, state->internal_comm.getBuffer()); break; default: