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model-checker : fix MC_RANDOM simcall
[simgrid.git] / src / mc / mc_state.c
1 /* Copyright (c) 2008-2012 Da SimGrid Team. All rights reserved.            */
2
3 /* This program is free software; you can redistribute it and/or modify it
4  * under the terms of the license (GNU LGPL) which comes with this package. */
5
6 #include "../simix/smx_private.h"
7 #include "xbt/fifo.h"
8 #include "mc_private.h"
9
10 /**
11  * \brief Creates a state data structure used by the exploration algorithm
12  */
13 mc_state_t MC_state_new()
14 {
15   mc_state_t state = NULL;
16   
17   state = xbt_new0(s_mc_state_t, 1);
18   state->max_pid = simix_process_maxpid;
19   state->proc_status = xbt_new0(s_mc_procstate_t, state->max_pid);
20   state->system_state = NULL;
21
22   mc_stats->expanded_states++;
23   return state;
24 }
25
26 mc_state_t MC_state_pair_new(void)
27 {
28   mc_state_t state = NULL;
29   
30   state = xbt_new0(s_mc_state_t, 1);
31   state->max_pid = simix_process_maxpid;
32   state->proc_status = xbt_new0(s_mc_procstate_t, state->max_pid);
33   
34   //mc_stats->expanded_states++;
35   return state;
36 }
37
38 /**
39  * \brief Deletes a state data structure
40  * \param trans The state to be deleted
41  */
42 void MC_state_delete(mc_state_t state)
43 {
44   if(state->system_state)
45     MC_free_snapshot(state->system_state);
46   xbt_free(state->proc_status);
47   xbt_free(state);
48 }
49
50 void MC_state_interleave_process(mc_state_t state, smx_process_t process)
51 {
52   state->proc_status[process->pid].state = MC_INTERLEAVE;
53   state->proc_status[process->pid].interleave_count = 0;
54 }
55
56 void MC_state_remove_interleave_process(mc_state_t state, smx_process_t process)
57 {
58   if(state->proc_status[process->pid].state == MC_INTERLEAVE)
59     state->proc_status[process->pid].state = MC_DONE;
60 }
61
62 unsigned int MC_state_interleave_size(mc_state_t state)
63 {
64   unsigned int i, size=0;
65
66   for(i=0; i < state->max_pid; i++){
67     if((state->proc_status[i].state == MC_INTERLEAVE) || (state->proc_status[i].state == MC_MORE_INTERLEAVE))
68       size++;
69   }
70
71   return size;
72 }
73
74 int MC_state_process_is_done(mc_state_t state, smx_process_t process){
75   return state->proc_status[process->pid].state == MC_DONE ? TRUE : FALSE;
76 }
77
78 void MC_state_set_executed_request(mc_state_t state, smx_simcall_t req, int value)
79 {
80   state->executed_req = *req;
81   state->req_num = value;
82   smx_process_t process = NULL;
83   mc_procstate_t procstate = NULL;
84
85   /* The waitany and testany request are transformed into a wait or test request over the
86    * corresponding communication action so it can be treated later by the dependence
87    * function. */
88   switch(req->call){
89     case SIMCALL_COMM_WAITANY:
90       state->internal_req.call = SIMCALL_COMM_WAIT;
91       state->internal_req.issuer = req->issuer;
92       state->internal_comm = *xbt_dynar_get_as(simcall_comm_waitany__get__comms(req), value, smx_action_t);
93       simcall_comm_wait__set__comm(&state->internal_req, &state->internal_comm);
94       simcall_comm_wait__set__timeout(&state->internal_req, 0);
95       break;
96
97     case SIMCALL_COMM_TESTANY:
98       state->internal_req.call = SIMCALL_COMM_TEST;
99       state->internal_req.issuer = req->issuer;
100
101       if(value > 0)
102         state->internal_comm = *xbt_dynar_get_as(simcall_comm_testany__get__comms(req), value, smx_action_t);
103
104       simcall_comm_test__set__comm(&state->internal_req, &state->internal_comm);
105       simcall_comm_test__set__result(&state->internal_req, value);
106       break;
107
108     case SIMCALL_COMM_WAIT:
109       state->internal_req = *req;
110       state->internal_comm = *(simcall_comm_wait__get__comm(req));
111       simcall_comm_wait__set__comm(&state->executed_req, &state->internal_comm);
112       simcall_comm_wait__set__comm(&state->internal_req, &state->internal_comm);
113       break;
114
115     case SIMCALL_COMM_TEST:
116       state->internal_req = *req;
117       state->internal_comm = *simcall_comm_test__get__comm(req);
118       simcall_comm_test__set__comm(&state->executed_req, &state->internal_comm);
119       simcall_comm_test__set__comm(&state->internal_req, &state->internal_comm);
120       break;
121
122     case SIMCALL_MC_RANDOM:
123       state->internal_req = *req;
124       simcall_mc_random__set__result(&state->internal_req, value);
125       if(value == 0){
126         xbt_swag_foreach(process, simix_global->process_list){
127           procstate = &state->proc_status[process->pid];
128           if(process->pid == req->issuer->pid){
129             procstate->state = MC_MORE_INTERLEAVE;  
130             break;
131           }        
132         }
133       }
134       break;
135
136     default:
137       state->internal_req = *req;
138       break;
139   }
140 }
141  
142 smx_simcall_t MC_state_get_executed_request(mc_state_t state, int *value)
143 {
144   *value = state->req_num;
145   return &state->executed_req;
146 }
147
148 smx_simcall_t MC_state_get_internal_request(mc_state_t state)
149 {
150   return &state->internal_req;
151 }
152
153 smx_simcall_t MC_state_get_request(mc_state_t state, int *value)
154 {
155   smx_process_t process = NULL;
156   mc_procstate_t procstate = NULL;
157   unsigned int start_count;
158
159   xbt_swag_foreach(process, simix_global->process_list){
160     procstate = &state->proc_status[process->pid];
161
162     if(procstate->state == MC_INTERLEAVE || procstate->state == MC_MORE_INTERLEAVE){
163       if(MC_process_is_enabled(process)){
164         switch(process->simcall.call){
165           case SIMCALL_COMM_WAITANY:
166             *value = -1;
167             while(procstate->interleave_count < xbt_dynar_length(simcall_comm_waitany__get__comms(&process->simcall))){
168               if(MC_request_is_enabled_by_idx(&process->simcall, procstate->interleave_count++)){
169                 *value = procstate->interleave_count-1;
170                 break;
171               }
172             }
173
174             if(procstate->interleave_count >= xbt_dynar_length(simcall_comm_waitany__get__comms(&process->simcall)))
175               procstate->state = MC_DONE;
176
177             if(*value != -1)
178               return &process->simcall;
179
180             break;
181
182           case SIMCALL_COMM_TESTANY:
183             start_count = procstate->interleave_count;
184             *value = -1;
185             while(procstate->interleave_count < xbt_dynar_length(simcall_comm_testany__get__comms(&process->simcall))){
186               if(MC_request_is_enabled_by_idx(&process->simcall, procstate->interleave_count++)){
187                 *value = procstate->interleave_count - 1;
188                 break;
189               }
190             }
191
192             if(procstate->interleave_count >= xbt_dynar_length(simcall_comm_testany__get__comms(&process->simcall)))
193               procstate->state = MC_DONE;
194
195             if(*value != -1 || start_count == 0)
196               return &process->simcall;
197
198             break;
199
200           case SIMCALL_COMM_WAIT:
201             if(simcall_comm_wait__get__comm(&process->simcall)->comm.src_proc
202                && simcall_comm_wait__get__comm(&process->simcall)->comm.dst_proc){
203               *value = 0;
204             }else{
205               *value = -1;
206             }
207             procstate->state = MC_DONE;
208             return &process->simcall;
209
210             break;
211
212           case SIMCALL_MC_RANDOM:
213             if(procstate->state == MC_INTERLEAVE)
214               *value = 0;
215             else
216               *value = 1;
217             procstate->state = MC_DONE;
218             return &process->simcall;
219             break;
220           
221           default:
222             procstate->state = MC_DONE;
223             *value = 0;
224             return &process->simcall;
225             break;
226         }
227       }
228     }
229   }
230
231   return NULL;
232 }